It is known in the art that semiconductor devices, particularly both bipolar and MOS (metal oxide semiconductor) transistor devices, tend to degrade with use. That is, for example, the transconductances G.sub.M of these devices undesirably continue to decrease after continued operation in the circuits. More specifically, for a given MOS transistor, a higher drain-to-source voltage V.sub.DS causes a higher rate of undesirable reduction of G.sub.M and hence a lower lifetime of useful operation (operational lifetime) of the transistor.
Each such device subject to this degradation is incorporated in a semiconductor body, typically silicon; and the device comprises a p-n junction, formed by the interface of two regions of the semiconductor body, one of the regions having a relatively high concentration of (conductivity-type determining) donor or acceptor impurities, the other having a relatively low concentration of acceptor or donor impurities, respectively--i.e., a p.sup.+ n or an n.sup.+ p junction, respectively. The p-n junction intersects the surface of the body at a location where the body is coated with an insulating layer. Degradation is believed to be caused by damage produced in the insulating layer by "hot" (fast-moving) charge carriers which are created in the region of relatively low impurity concentration, particularly in the neighborhood of the intersection of the p-n junction with the surface of the body. Accordingly, because of the higher electric fields which are ordinarily present in smaller sized devices and which cause a more severe hot charge carrier problem, smaller sized devices tend to have lower operational lifetimes.
In U.S. Pat. No. 4,704,547 issued to H. Kirsch on Nov. 3, 1987, entitled "IGFET Gating Circuit Having Reduced Electric Field Degradation," it was taught that the degradation of MOS transistors due to hot carriers could be alleviated in complementary transistor logic gates by the technique of inserting an extra (protective) transistor between the p-channel and n-channel transistors. However, the technique of that patent requires the added transistor, which may be undesirable from the standpoints of speed performance and of consuming precious semiconductor surface area, particularly in complex logic circuits; and the technique may not be convenient to use in the context of circuits other than complementary transistor logic gates and the like.
Another technique for reducing MOS transistor degradation is the lightly doped drain (LDD), in which the concentration of conductivity-type determining impurities is reduced in a neighborhood of the drain. However, in this technique unwanted added series resistance in the drain outside the transistor channel is unavoidable, whereby the switching speed of the transistor is undesirably reduced, especially when the added resistance is comparable to the resistance of the channel itself, as is the case where the channel length is approximately 0.5 micrometer or less.
Yet another technique for coping with the hot carrier problem is a reduction in drain-source operating voltages. This technique, however, entails not only loss of speed but also a reduction in tolerable noise margins. Moreover, in case the channel length goes to approximately 0.5 micrometer or less, the reduction in drain-source operating voltages would present a serious obstacle to the use of Bipolar Complementary MOS (BiCMOS) circuits because of the higher minimum operating voltage requirements of the bipolar transistors in such circuits.
It would therefore be desirable to have a technique for reducing the rate of degradation (increase the operational lifetime) of MOS transistors, which does not suffer from the aforementioned problems.